1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device with a stacked-bank architecture that enables decoded row address signals with respect to each of a plurality of banks, and activates word lines coupled to memory cells with respect to each of the plurality of banks.
2. Description of the Related Art
A semiconductor memory device such as a DRAM (Dynamic Random Access Memory) comprises an array of memory cells arranged in rows and columns. An intersection of a row and a column defines an address of a memory cell location. In general, each of the memory cells comprises a capacitor for storing charge and a transistor for gating that charge onto a bit line. A charge is a representation of a data bit, and the charge stored in the capacitor determines whether the bit is considered a logic “1” or a logic “0”. In general, a high voltage represents a logic “1” and a low voltage represents a logic “0”. Data may be stored in the memory during a write operation, and may be read out during a read operation.
A capacitor is charged when the data is stored in the DRAM cell in the write cycle, and the amount of charge stored in the capacitor is sensed to estimate the logic state of the memory cell when the data is read out from the memory cell in the subsequent read cycle. However, a general DRAM needs a so-called “refresh operation” because the capacitor in the memory cell is subject to charge leakage so that the data stored will be lost, unless the charge is refreshed periodically. Refresh logic is commonly used with DRAMs to automate the periodic refresh.
In the conventional DRAM, during a read of any memory cell, the entire row is read out and written back in (refresh); during a write to any memory cell, the entire row is read out, one value is changed, and the entire row is written back in. Data may be read by activating the row that is called a “word line”.
A word line couples all the memory cells that belong to the row to the bit lines that define the columns of the memory array. When a particular word line is activated, a sense amplifier detects and amplifies the data that is in the activated bit/column line. The sense amplifier senses whether logic “1” or logic “0” is stored in the memory location.
One method to improve an access time and a cycle time is to decrease the length of each word line and to decrease the number of word lines per memory cell array. That is, the method improves the access time by decreasing the capacitance load generated by the word lines. To implement this method, the technology for forming multiple banks by arranging the DRAM memory cells in operational units or “banks” was widely adopted. Generally, address buses, arranged in the peripheral circuit area or “backbone”, transfer memory cell addresses and data for read, write, and refresh operations in each of the banks.
A semiconductor memory device having a stacked-bank architecture has been designed to reduce power consumption. FIG. 1 is a block diagram illustrating a conventional DRAM having a stacked-bank architecture. Referring to FIG. 1, a DRAM includes memory bank groups 100, 200, 300, and 400 (shown by dashed lines), and a decoder unit 500. The memory bank groups 100, 200, 300, and 400 are comprised of memory banks. For example, the memory bank group 100 is comprised of memory banks (BANK 1A) 110, (BANK 1B) 120, (BANK 1C) 130, and (BANK 1D) 140. Each of the memory bank groups 100, 200, 300, and 400 activates word lines of a memory cell array in response to the decoded row address signal DRAij.
The decoder unit 500 generates the row address signal DRAij in response to an external address signal XRA. Referring to FIG. 1, the row address signal DRAij outputted from the decoder unit 500 is transferred to all of the memory banks within a memory bank group.
FIG. 2 is a detailed circuit diagram illustrating a memory bank group in the DRAM of FIG. 1. Referring to FIG. 2, the memory bank 100 includes memory banks 110, 120, 130, and 140. Each of the memory banks 110, 120, 130, and 140 includes a main decoder unit (116, 126, 136 and 146, respectively), a word line driving unit (114, 124, 134 and 144, respectively) and a memory cell array (112, 122, 132 and 142, respectively). The decoded row address signal DRAij is not only applied to the main decoder 116 that is in the memory bank 110, but also applied to the main decoder 126 that is in the memory bank 120. Further, the decoded row address signal DRAij is not only applied to the main decoder 136 that is in the memory bank 130, but also applied to the main decoder 146 that is in the memory bank 140.
The signals PA, PB, PC, and PD that have memory bank information are applied to the main decoder unit 116, 126, 136, and 146 to activate or inactivate word lines.
Referring to FIG. 1 and FIG. 2, in the conventional semiconductor memory device having a stacked-bank architecture, signal lines reaching word lines of all the memory banks are activated simultaneously because the decoded row address signal DRAij is transferred to all of the memory banks within a memory bank group. Therefore, the device consumes electric power unnecessarily. In addition, as shown in FIG. 1, in the conventional semiconductor memory device having a stacked-bank architecture, the length of a signal line reaching each memory bank, e.g., BANK 1A, BANK 2A, BANK 3A or BANK 4A, is different. If the length of signal line is not matched with respect to the memory banks, the semiconductor memory device may not operate normally when noise is generated.